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BS IEC 62566-2:2020 Nuclear power plants. Instrumentation and control important to safety. Development of HDL-programmed integrated circuits - HDL-programmed integrated circuits for systems performing category B or C functions, 2020
- undefined
- English [Go to Page]
- CONTENTS
- FOREWORD
- INTRODUCTION
- 1 Scope
- 2 Normative references
- 3 Terms and definitions
- 4 Symbols and abbreviated terms
- 5 General requirements for HPD projects [Go to Page]
- 5.1 General
- 5.2 Life-cycle
- Figures [Go to Page]
- Figure 1 – System life-cycle (informative, as defined by IEC 61513)
- 5.3 Gradation principles
- Figure 2 – HPD life-cycle
- 5.4 HPD quality assurance [Go to Page]
- 5.4.1 General
- 5.5 Configuration management [Go to Page]
- 5.5.1 General
- 5.6 HPD Verification
- 6 HPD requirements specification [Go to Page]
- 6.1 General [Go to Page]
- 6.1.1 Overview
- 6.2 Functional aspects of the requirements specification [Go to Page]
- 6.2.1 General
- 6.3 Fault detection and fault tolerance
- 6.4 Requirements capture using Electronic System Level tools [Go to Page]
- 6.4.1 General
- 6.4.2 Requirements on the formalism of tools used at ESL level
- 6.4.3 Interface with design tools
- 7 Acceptance process for programmable integrated circuits, native blocks and Pre-Developed Blocks [Go to Page]
- 7.1 General
- 7.2 Acceptance process for programmable integrated circuits and included native blocks [Go to Page]
- 7.2.1 General
- 7.2.2 Integrated Circuit acceptance
- Figure 3 – Overview of selection and acceptance processfor blank Integrated Circuits and native blocks
- 7.3 Acceptance process for PDBs [Go to Page]
- 7.3.1 General
- 7.3.2 PDB functional suitability
- Figure 4 – Overview of selection and acceptance process for PDBs [Go to Page]
- 7.3.3 Documentation for safety of PDBs
- 7.3.4 Generation of supporting documentation for safety
- 7.3.5 Complementary means
- 7.3.6 Rules of use
- 7.3.7 Modification for acceptance
- 8 HPD design and implementation [Go to Page]
- 8.1 General
- 8.2 Hardware Description Languages (HDL) and related tools [Go to Page]
- 8.2.1 General
- 8.3 Design [Go to Page]
- 8.3.1 General
- 8.3.2 Fault detection
- 8.3.3 Language and coding rules
- 8.3.4 Synchronous vs. asynchronous design
- 8.3.5 Power Management
- 8.3.6 Design documentation
- 8.4 Implementation [Go to Page]
- 8.4.1 Products
- 8.4.2 Files of parameters and constraints
- 8.4.3 Post-route analyses
- 8.4.4 Redundancies introduced or removed by the tools
- 8.4.5 Finite state machines
- 8.4.6 Static Timing Analysis
- 8.4.7 Implementation documentation
- 8.5 System level tools and automated code generation [Go to Page]
- 8.5.1 General
- 9 HPD integration and testing [Go to Page]
- 9.1 General
- 9.2 Test-benches for HPD functional simulation
- 9.3 Test coverage
- 9.4 Test execution
- 10 HPD aspects of system integration [Go to Page]
- 10.1 General
- 10.2 Requirements
- 11 HPD aspects of system validation [Go to Page]
- 11.1 General
- 11.2 Requirements
- 12 Modification [Go to Page]
- 12.1 Modification of the requirements, design or implementation [Go to Page]
- 12.1.1 General
- 12.2 Modification of the micro-electronic technology
- 13 HPD production [Go to Page]
- 13.1 General
- 13.2 Production tests
- 13.3 Programming files and programming activities
- 14 HPD aspects of installation, commissioning and operation [Go to Page]
- 14.1 General [Go to Page]
- 14.1.1 Overview
- 14.2 Anomaly reports
- 15 Software tools for the development of HPDs [Go to Page]
- 15.1 General [Go to Page]
- 15.1.1 Overview
- 15.2 Additional requirements for design, implementation and simulation tools
- 16 Design segmentation or partitioning [Go to Page]
- 16.1 Background
- 16.2 Auxiliary or support functions [Go to Page]
- 16.2.1 General
- 16.2.2 Partitioning of auxiliary or support functions or functions of an inferior safety category
- 17 Defences against HPD Common Cause Failure
- Annex A (informative)Documentation [Go to Page]
- A.1 General
- A.2 Project
- A.3 HPD requirement specification
- A.4 Acceptance of blank integrated circuits, Native Blocks and PDBs
- A.5 HPD design and implementation
- A.6 HPD integration and testing
- A.7 HPD aspects of system integration
- A.8 HPD aspects of system validation
- A.9 Modification
- A.10 HPD production
- A.11 Software tools for the development of HPDs
- Annex B (informative)Development of HPDs [Go to Page]
- B.1 General
- B.2 Optional capture of requirements at Electronic System Level
- B.3 HPD and system life-cycle
- B.4 Design
- B.5 Acceptance process for programmable integrated circuits, native blocks and Pre-Developed Blocks
- B.6 Implementation
- B.7 HPD integration and testing
- B.8 Types of specific integrated circuits [Go to Page]
- B.8.1 General
- B.8.2 PAL (Programmable Array Logic)
- B.8.3 PLD, CPLD (Programmable Logic Device, Complex PLD)
- B.8.4 FPGA
- B.8.5 Gate Array, or pre-diffused integrated circuit
- B.8.6 Standard Cells
- B.8.7 “Full custom ASIC”, or “raw ASIC”
- Bibliography [Go to Page]