Already a subscriber?
MADCAD.com Free Trial
Sign up for a 3 day free trial to explore the MADCAD.com interface, PLUS access the
2009 International Building Code to see how it all works.
If you like to setup a quick demo, let us know at support@madcad.com
or +1 800.798.9296 and we will be happy to schedule a webinar for you.
Security check
Please login to your personal account to use this feature.
Please login to your authorized staff account to use this feature.
Are you sure you want to empty the cart?
IEC/IEEE International Standard - Behavioural Languages - Part 4: Verilog(C) Hardware Description Language, 2004
- CONTENTS
- Foreword
- IEEE Introduction
- 1. Overview [Go to Page]
- 1.1 Objectives of this standard
- 1.2 Conventions used in this standard
- 1.3 Syntactic description
- 1.4 Contents of this standard
- 1.5 Header file listings
- 1.6 Examples
- 1.7 Prerequisites
- 2. Lexical conventions [Go to Page]
- 2.1 Lexical tokens
- 2.2 White space
- 2.3 Comments
- 2.4 Operators
- 2.5 Numbers
- 2.6 Strings
- 2.7 Identifiers, keywords, and system names
- 2.8 Attributes
- 3. Data types [Go to Page]
- 3.1 Value set
- 3.2 Nets and variables
- 3.3 Vectors
- 3.4 Strengths
- 3.5 Implicit declarations
- 3.6 Net initialization
- 3.7 Net types
- 3.8 regs
- 3.9 Integers, reals, times, and realtimes
- 3.10 Arrays
- 3.11 Parameters
- 3.12 Name spaces
- 4. Expressions [Go to Page]
- 4.1 Operators
- 4.2 Operands
- 4.3 Minimum, typical, and maximum delay expressions
- 4.4 Expression bit lengths
- 4.5 Signed expressions
- 5. Scheduling semantics [Go to Page]
- 5.1 Execution of a model
- 5.2 Event simulation
- 5.3 The stratified event queue
- 5.4 The Verilog simulation reference model
- 5.5 Race conditions
- 5.6 Scheduling implication of assignments
- 6. Assignments [Go to Page]
- 6.1 Continuous assignments
- 6.2 Procedural assignments
- 7. Gate and switch level modeling [Go to Page]
- 7.1 Gate and switch declaration syntax
- 7.2 and, nand, nor, or, xor, and xnor gates
- 7.3 buf and not gates
- 7.4 bufif1, bufif0, notif1, and notif0 gates
- 7.5 MOS switches
- 7.6 Bidirectional pass switches
- 7.7 CMOS switches
- 7.8 pullup and pulldown sources
- 7.9 Logic strength modeling
- 7.10 Strengths and values of combined signals
- 7.11 Strength reduction by nonresistive devices
- 7.12 Strength reduction by resistive devices
- 7.13 Strengths of net types
- 7.14 Gate and net delays
- 8. User-defined primitives (UDPs) [Go to Page]
- 8.1 UDP definition
- 8.2 Combinational UDPs
- 8.3 Level-sensitive sequential UDPs
- 8.4 Edge-sensitive sequential UDPs
- 8.5 Sequential UDP initialization
- 8.6 UDP instances
- 8.7 Mixing level-sensitive and edge-sensitive descriptions
- 8.8 Level-sensitive dominance
- 9. Behavioral modeling [Go to Page]
- 9.1 Behavioral model overview
- 9.2 Procedural assignments
- 9.3 Procedural continuous assignments
- 9.4 Conditional statement
- 9.5 Case statement
- 9.6 Looping statements
- 9.7 Procedural timing controls
- 9.8 Block statements
- 9.9 Structured procedures
- 10. Tasks and functions [Go to Page]
- 10.1 Distinctions between tasks and functions
- 10.2 Tasks and task enabling
- 10.3 Functions and function calling
- 11. Disabling of named blocks and tasks
- 12. Hierarchical structures [Go to Page]
- 12.1 Modules
- 12.2 Overriding module parameter values
- 12.3 Ports
- 12.4 Hierarchical names
- 12.5 Upwards name referencing
- 12.6 Scope rules
- 13. Configuring the contents of a design [Go to Page]
- 13.1 Introduction
- 13.2 Libraries
- 13.3 Configurations
- 13.4 Using libraries and configs
- 13.5 Configuration examples
- 13.6 Displaying library binding information
- 13.7 Library mapping examples
- 14. Specify blocks [Go to Page]
- 14.1 Specify block declaration
- 14.2 Module path declarations
- 14.3 Assigning delays to module paths
- 14.4 Mixing module path delays and distributed delays
- 14.5 Driving wired logic
- 14.6 Detailed control of pulse filtering behavior
- 15. Timing checks [Go to Page]
- 15.1 Overview
- 15.2 Timing checks using a stability window
- 15.3 Timing checks for clock and control signals
- 15.4 Edge-control specifiers
- 15.5 Notifiers: user-defined responses to timing violations
- 15.6 Enabling timing checks with conditioned events
- 15.7 Vector signals in timing checks
- 15.8 Negative timing checks
- 16. Backannotation using the Standard Delay Format (SDF) [Go to Page]
- 16.1 The SDF annotator
- 16.2 Mapping of SDF constructs to Verilog
- 16.3 Multiple annotations
- 16.4 Multiple SDF files
- 16.5 Pulse limit annotation
- 16.6 SDF to Verilog delay value mapping
- 17. System tasks and functions [Go to Page]
- 17.1 Display system tasks
- 17.2 File input-output system tasks and functions
- 17.3 Timescale system tasks
- 17.4 Simulation control system tasks
- 17.5 PLA modeling system tasks
- 17.6 Stochastic analysis tasks
- 17.7 Simulation time system functions
- 17.8 Conversion functions
- 17.9 Probabilistic distribution functions
- 17.10 Command line input
- 18. Value change dump (VCD) files [Go to Page]
- 18.1 Creating the four state value change dump file
- 18.2 Format of the four state VCD file
- 18.3 Creating the extended value change dump file
- 18.4 Format of the extended VCD file
- 19. Compiler directives [Go to Page]
- 19.1 `celldefine and `endcelldefine
- 19.2 `default_nettype
- 19.3 `define and `undef
- 19.4 `ifdef, `else, `elsif, `endif, `ifndef
- 19.5 `include
- 19.6 `resetall
- 19.7 `line
- 19.8 `timescale
- 19.9 `unconnected_drive and `nounconnected_drive
- 20. PLI overview [Go to Page]
- 20.1 PLI purpose and history (informative)
- 20.2 User-defined system task or function names
- 20.3 User-defined system task or function types
- 20.4 Overriding built-in system task and function names
- 20.5 User-supplied PLI applications
- 20.6 PLI interface mechanism
- 20.7 User-defined system task and function arguments
- 20.8 PLI include files
- 20.9 PLI Memory Restrictions
- 21. PLI TF and ACC interface mechanism [Go to Page]
- 21.1 User-supplied PLI applications
- 21.2 Associating PLI applications to a class and system task/function name
- 21.3 PLI application arguments
- 22. Using ACC routines [Go to Page]
- 22.1 ACC routine definition
- 22.2 The handle data type
- 22.3 Using ACC routines
- 22.4 List of ACC routines by major category
- 22.5 Accessible objects
- 22.6 ACC routine types and fulltypes
- 22.7 Error handling
- 22.8 Reading and writing delay values
- 22.9 String handling
- 22.10 Using VCL ACC routines
- 23. ACC routine definitions
- 24. Using TF routines [Go to Page]
- 24.1 TF routine definition
- 24.2 TF routine system task/function arguments
- 24.3 Reading and writing system task/function argument values
- 24.4 Value change detection
- 24.5 Simulation time
- 24.6 Simulation synchronization
- 24.7 Instances of user-defined tasks or functions
- 24.8 Module and scope instance names
- 24.9 Saving information from one system TF call to the next
- 24.10 Displaying output messages
- 24.11 Stopping and finishing
- 25. TF routine definitions
- 26. Using VPI routines [Go to Page]
- 26.1 VPI system tasks and functions
- 26.2 The VPI interface
- 26.3 VPI object classifications
- 26.4 List of VPI routines by functional category
- 26.5 Key to data model diagrams
- 27. VPI routine definitions
- Annex A (normative) Formal syntax definition
- Annex B (normative) List of keywords
- Annex C (informative) System tasks and functions
- Annex D (informative) Compiler directives
- Annex E (normative) acc_user.h
- Annex F (normative) veriuser.h
- Annex G (normative) vpi_user.h
- Annex H (informative) Bibliography
- Annex I (informative) List of Participants [Go to Page]