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IEEE Standard for Information technology-- Local and metropolitan area networks-- Part 3: CSMA/CD Access Method and Physical Layer Specifications Amendment 7: Media Access Control (MAC) Service Interface and Management Parameters to Support Time Synchroni, 2011
- IEEE Std 802.3bf™-2011, Front cover
- Title page
- Introduction
- Notice to users [Go to Page]
- Laws and regulations
- Copyrights
- Updating of IEEE documents
- Errata
- Downloads
- Interpretations
- Contents
- Participants
- IMPORTANT NOTICE
- 1. Introduction [Go to Page]
- 1.4 Definitions
- 1.5 Abbreviations
- 30. Management [Go to Page]
- 30.2.2.1 Text description of managed objects
- 30.2.3 Containment
- 30.2.5 Capabilities
- 30.13 Management for oTimeSync entity [Go to Page]
- 30.13.1 TimeSync entity managed object class [Go to Page]
- 30.13.1.1 aTimeSyncCapabilityTX
- 30.13.1.2 aTimeSyncCapabilityRX
- 30.13.1.3 aTimeSyncDelayTXmax
- 30.13.1.4 aTimeSyncDelayTXmin
- 30.13.1.5 aTimeSyncDelayRXmax
- 30.13.1.6 aTimeSyncDelayRXmin
- 45. Management Data Input/Output (MDIO) Interface [Go to Page]
- 45.2.1 PMA/PMD registers [Go to Page]
- 45.2.1.100 TimeSync PMA/PMD capability (Register 1.1800)
- 45.2.1.101 TimeSync PMA/PMD transmit path data delay (Registers 1.1801, 1.1802, 1.1803, 1.1804)
- 45.2.1.102 TimeSync PMA/PMD receive path data delay (Registers 1.1805, 1.1806, 1.1807, 1.1808)
- 45.2.2 WIS registers [Go to Page]
- 45.2.2.20 TimeSync WIS capability (Register 2.1800)
- 45.2.2.21 TimeSync WIS transmit path data delay (Registers 2.1801, 2.1802, 2.1803, 2.1804)
- 45.2.2.22 TimeSync WIS receive path data delay (Registers 2.1805, 2.1806, 2.1807, 2.1808)
- 45.2.3 PCS registers [Go to Page]
- 45.2.3.40 TimeSync PCS capability (Register 3.1800)
- 45.2.3.41 TimeSync PCS transmit path data delay (Registers 3.1801, 3.1802, 3.1803, 3.1804)
- 45.2.3.42 TimeSync PCS receive path data delay (Registers 3.1805, 3.1806, 3.1807, 3.1808)
- 45.2.4 PHY XS registers [Go to Page]
- 45.2.4.10 TimeSync PHY XS capability (Register 4.1800)
- 45.2.4.11 TimeSync PHY XS transmit path data delay (Registers 4.1801, 4.1802, 4.1803, 4.1804)
- 45.2.4.12 TimeSync PHY XS receive path data delay (Registers 4.1805, 4.1806, 4.1807, 4.1808)
- 45.2.5 DTE XS registers [Go to Page]
- 45.2.5.10 TimeSync DTE XS capability (Register 5.1800)
- 45.2.5.11 TimeSync DTE XS transmit path data delay (Registers 5.1801, 5.1802, 5.1803, 5.1804)
- 45.2.5.12 TimeSync DTE XS receive path data delay (Registers 5.1805, 5.1806, 5.1807, 5.1808)
- 45.2.6 TC registers [Go to Page]
- 45.2.6.14 TimeSync TC capability (Register 6.1800)
- 45.2.6.15 TimeSync TC transmit path data delay (Registers 6.1801, 6.1802, 6.1803, 6.1804)
- 45.2.6.16 TimeSync TC receive path data delay (Registers 6.1805, 6.1806, 6.1807, 6.1808)
- 90. Ethernet Support for Time Synchronization Protocols [Go to Page]
- 90.1 Introduction
- 90.2 Overview
- 90.3 Relationship with other IEEE standards
- 90.4 Time Synchronization Service Interface (TSSI) [Go to Page]
- 90.4.1 Introduction [Go to Page]
- 90.4.1.1 Interlayer service interfaces
- 90.4.1.2 Responsibilities of TimeSync Client
- 90.4.2 TSSI
- 90.4.3 Detailed service specification [Go to Page]
- 90.4.3.1 TS_TX.indication primitive [Go to Page]
- 90.4.3.1.1 Semantics
- 90.4.3.1.2 Condition for generation
- 90.4.3.1.3 Effect of receipt
- 90.4.3.2 TS_RX.indication primitive [Go to Page]
- 90.4.3.2.1 Semantics
- 90.4.3.2.2 Condition for generation
- 90.4.3.2.3 Effect of receipt
- 90.5 generic Reconciliation Sublayer (gRS) [Go to Page]
- 90.5.1 TS_SFD_Detect_TX function
- 90.5.2 TS_SFD_Detect_RX function
- 90.6 Overview of management features
- 90.7 Data delay measurement
- 90.8 Protocol implementation conformance statement (PICS) proforma for Clause 90, Ethernet Support for Time Synchronization Protocols [Go to Page]
- 90.8.1 Introduction
- 90.8.2 Identification [Go to Page]
- 90.8.2.1 Implementation identification
- 90.8.2.2 Protocol summary
- 90.8.3 TSSI indication
- 90.8.4 Data delay reporting
- Annex A (informative) Bibliography [Go to Page]