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eLibrary > BS EN IEC 62271-101:2021 High-voltage switchgear and controlgear - Synthetic testing >

BS EN IEC 62271-101:2021 High-voltage switchgear and controlgear - Synthetic testing, 2022

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BS EN IEC 62271-101:2021 High-voltage switchgear and controlgear - Synthetic testing, 2022

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National foreword
Annex ZA(normative)Normative references to international publicationswith their corresponding European publications
English [Go to Page]
CONTENTS
FOREWORD
1 Scope
2 Normative references
3 Terms and definitions
4 Synthetic testing techniques and methods for short-circuit breaking tests [Go to Page]
4.1 Basic principles and general requirements for synthetic breaking test methods [Go to Page]
4.1.1 General
4.1.2 High-current interval
Figures [Go to Page]
Figure 1 – Interrupting process – Basic time intervals [Go to Page]
4.1.3 Interaction interval
4.1.4 High-voltage interval
Tables [Go to Page]
Table 1 – Tolerances and limits required during the high-current interval
Figure 2 – Examples of evaluation of initial recovery voltage
4.2 Synthetic test circuits and related specific requirements for breaking tests [Go to Page]
4.2.1 Current injection methods
4.2.2 Voltage injection method
Figure 3 – Equivalent surge impedance of the voltage circuit for the current injection method [Go to Page]
4.2.3 Duplicate circuit method (transformer or Skeats circuit)
4.2.4 Other synthetic test methods
4.3 Three-phase synthetic test methods
Table 2 – Test circuits for test duties T100s and T100a
Table 3 – Test parameters during three-phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,5
Figure 4 – Reference lines of TRV with four-parameter for kpp = 1,5
Table 4 – Test parameters during three-phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,3
Figure 5 – Reference lines of TRV with four-parameter for kpp = 1,3
Table 5 – Test parameters during three phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,2
5 Synthetic testing techniques and methods for short-circuit making tests [Go to Page]
5.1 Basic principles and general requirements for synthetic making test methods [Go to Page]
5.1.1 General
Figure 6 – Reference lines of TRV with four-parameter for kpp = 1,2
Figure 7 – Making process – Basic time intervals [Go to Page]
5.1.2 High-voltage interval
5.1.3 Pre-arcing interval
5.1.4 Latching interval and fully closed position
5.2 Synthetic test circuit and related specific requirements for making tests [Go to Page]
5.2.1 General
5.2.2 Test circuit and test requirements
Figure 8 – Example of synthetic making circuit for single-phase tests
Figure 9 – Example of synthetic making circuit for out-of-phase tests
Figure 10 – Example of synthetic making circuit for three-phase tests (kpp = 1,5) [Go to Page]
5.2.3 Alternative test method with reduced voltage
7 Type tests [Go to Page]
7.102 General
Table 6 – Symbols and abbreviated terms used for operation during synthetic tests
7.104 Demonstration of arcing times
Figure 11 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic (right) for T100s with kpp = 1,5
Figure 12 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic (right) for T100s with kpp = 1,3
Figure 13 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic tests (right) for T100a with kpp = 1,5
Figure 14 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic tests (right) for T100a with kpp = 1,3
7.107 Terminal fault tests
Table 7 – Synthetic test methods for test duties T10, T30, T60,T100s, T100a, SP, DEF, OP and SLF
7.109 Short-line fault tests
7.110 Out-of-phase making and breaking tests
7.111 Capacitive current tests
Figure 15 – Evaluation of recovery voltage during synthetic capacitive current switching testing
Annexes [Go to Page]
Annex A (normative) Correction of di/dt and TRV for test duty T100a [Go to Page]
A.1 General
A.2 Reduction in di/dt
A.3 Corrected TRV for the first-pole-to-clear with required asymmetry
Table A.1 – Corrected TRV values for the first-pole-to-clear for kpp = 1,3 and fr = 50 Hz
Table A.2 – Corrected TRV values for the first-pole-to-clear for kpp = 1,3 and fr = 60 Hz
Table A.3 – Corrected TRV values for the first-pole-to-clear for kpp = 1,5 and fr = 50 Hz
Table A.4 – Corrected TRV values for the first-pole-to-clear for kpp = 1,5 and fr = 60 Hz
Table A.5 – Corrected TRV values for the first-pole-to-clear for kpp = 1,2 and fr = 50 Hz
Table A.6 – Corrected TRV values for the first-pole-to-clear for kpp = 1,2 and fr = 60 Hz
Table A.7 – Percentage of DC component and di/dt at current zero for first-pole-to-clear for fr = 50 Hz [Go to Page]
A.4 Correction of the di/dt and TRV of the first-pole-to-clear for tests with intermediate asymmetry
Table A.8 – Percentage of DC component and di/dt at current zero for first-pole-to-clear for fr = 60 Hz [Go to Page]
A.5 Correction of the di/dt and TRV of the second- or last-pole-to-clear with major extended loop with required asymmetry during three-phase tests
A.6 Correction of the di/dt and TRV during tests with a subsequent minor loop
A.7 Calculation of the di/dt and TRV of the first-pole-to-clear [Go to Page]
A.7.1 General
A.7.2 Calculation of di/dt
A.7.3 Calculation of TRV
A.7.4 Examples of calculation of di/dt and TRV
Annex B (normative) Tolerances on test quantities for type tests
Table B.1 – Tolerances on test quantities for type tests
Annex C (normative) Information to be given and results to be recorded for synthetic tests [Go to Page]
C.1 General
C.2 Auxiliary circuit-breaker
C.3 Test conditions
C.4 Quantities to be recorded [Go to Page]
C.4.1 General
C.4.2 Voltages
C.4.3 Currents
Annex D (normative) Test procedure using a three-phase current circuit and one voltage circuit [Go to Page]
D.1 Test circuit
D.2 Test method [Go to Page]
D.2.1 General
D.2.2 Test duty T100s(b)
Figure D.1 – Example of a three-phase current circuit with single-phase synthetic injection
Table D.1 – Demonstration of arcing times for kpp = 1,5
Figure D.2 – Representation of the testing conditions of Table D.1
Table D.2 – Alternative demonstration of arcing times for kpp = 1,5
Figure D.3 – Representation of the testing conditions of Table D.2
Table D.3 – Demonstration of arcing times for kpp = 1,3
Figure D.4 – Representation of the testing conditions of Table D.3
Table D.4 – Alternative demonstration of arcing times for kpp = 1,3
Figure D.5 – Representation of the testing conditions of Table D.4 [Go to Page]
[Go to Page]
D.2.3 Test duty T100a
Table D.5 – Demonstration of arcing times for kpp = 1,5
Figure D.6 – Representation of the testing conditions of Table D.5
Table D.6 – Alternative demonstration of arcing times for kpp = 1,5
Figure D.7 – Representation of the testing conditions of Table D.6
Table D.7 – Demonstration of arcing times for kpp = 1,3
Figure D.8 – Representation of the testing conditions of Table D.7
Table D.8 – Alternative demonstration of arcing times for kpp = 1,3
Figure D.9 – Representation of the testing conditions of Table D.8 [Go to Page]
[Go to Page]
D.2.4 Combination of first-pole-to-clear factors 1,3 and 1,5
Table D.9 – Procedure for combining kpp = 1,5 and 1,3 during test-duties T10, T30, T60 and T100s(b)
Table D.10 – Procedure for combining kpp = 1,5 and 1,3 during test-duty T100a
Annex E (normative) Splitting of test duties in test series taking into account the associated TRV for each pole-to-clear [Go to Page]
E.1 General
E.2 Test-duties T10, T30, T60, T100s(b), OP1 and OP2(b) [Go to Page]
E.2.1 Test procedure for first-pole-to-clear factors 1,5 and 2,5
Table E.1 – Test procedure for kpp = 1,5 and 2,5 [Go to Page]
[Go to Page]
E.2.2 Test procedure for first-pole-to-clear factors 1,3 and 2,0
Table E.2 – Test procedure for kpp = 1,3 and 2,0 [Go to Page]
[Go to Page]
E.2.3 Test procedure for first-pole-to-clear factor 1,2
Table E.3 – Simplified test procedure for kpp = 1,3 and 2,0 [Go to Page]
E.3 Test duty T100a [Go to Page]
E.3.1 General
Table E.4 – Test procedure for kpp = 1,2
Table E.5 – Simplified test procedure for kpp = 1,2 [Go to Page]
[Go to Page]
E.3.2 Test procedure for first-pole-to-clear factor 1,5
Table E.6 – Test procedure for asymmetrical currents for kpp = 1,5 [Go to Page]
[Go to Page]
E.3.3 Test procedure for first-pole-to-clear factor 1,3
Figure E.1 – Example of graphical representation of the tests shown in Table E.6
Table E.7 – Test procedure for asymmetrical currents for kpp = 1,3 [Go to Page]
[Go to Page]
E.3.4 Test procedure for first-pole-to-clear factor 1,2
Figure E.2 – Example of graphical representation of the tests shown in Table E.7 and Table E.8 [Go to Page]
E.4 Combination of first-pole-to-clear factors [Go to Page]
E.4.1 General
E.4.2 Combination of first-pole-to-clear factors 1,3 and 1,5 for test duties T10, T30, T60 and T100s(b)
Table E.8 – Test procedure for asymmetrical currents for kpp = 1,2 [Go to Page]
[Go to Page]
E.4.3 Combination of first-pole-to-clear factors 2,0 and 2,5 for test duties OP1 and OP2(b)
Table E.9 – Procedure for combining kpp = 1,3 and 1,5 for test-duties T10, T30, T60 and T100s(b) [Go to Page]
[Go to Page]
E.4.4 Combination of first-pole-to-clear factors 1,3 and 1,5 for test duty T100a
Table E.10 – Procedure for combining kpp = 2,0 and 2,5 for test-duties OP1 and OP2(b)
Table E.11 – Procedure for combining kpp = 1,5 and 1,3 for test-duty T100a
Table E.12 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,5, fr = 50 Hz
Table E.13 – Required test parameters for different asymmetrical conditions in the case of a kpp = 1,3, fr = 50 Hz
Table E.14 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,2, fr = 50 Hz
Table E.15 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,5, fr = 60 Hz
Table E.16 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,3, fr = 60 Hz
Table E.17 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,2, fr = 60 Hz
Annex F (informative) Three-phase synthetic test circuits [Go to Page]
F.1 General
F.2 Three-phase synthetic combined circuit
Figure F.1 – Three-phase synthetic combined circuit
Figure F.2 – Waveshapes of currents, phase-to-ground and phase-to phase voltages during a three-phase synthetic test (T100s; kpp = 1,5) performed according to the three-phase synthetic combined circuit [Go to Page]
F.3 Three-phase synthetic circuit with injection in all phases
Figure F.3 – Three-phase synthetic circuit with injection in all phases for kpp = 1,5 [Go to Page]
F.4 Three-phase synthetic circuit with injection in two phases
Figure F.4 – Waveshapes of currents and phase-to-ground voltages during a three-phase synthetic test (T100s; kpp = 1,5) performed according to the three-phase synthetic circuit with injection in all phases
Figure F.5 – Three-phase synthetic circuit for terminal fault tests with kpp = 1,3 (current injection method)
Figure F.6 – Waveshapes of currents and phase-to-ground voltages during a three phase synthetic test (T100s; kpp = 1,3 ) performed according to the three-phase synthetic circuit shown in Figure F.5
Figure F.7 – TRV voltages waveshapes of the test circuit described in Figure F.5
Annex G (informative) Examples of test circuits for metal-enclosed and dead tank circuit-breakers
Figure G.1 – Example of a test circuit for unit testing (circuit-breaker with interaction due to gas circulation)
Figure G.2 – Oscillogram corresponding to Figure G.1 –Example of the required TRVs to be applied between the terminals of the unit(s) under test and between the live parts and the insulated enclosure
Figure G.3 – Example of test circuit using two voltage circuits for breaking tests
Figure G.4 – Example of test circuit using two voltage circuits for breaking tests
Figure G.5 – Example of a synthetic test circuit for unit testing (if unit testing is allowed as per 7.102.4.2 of IEC 62271-100:2021)
Figure G.6 – Oscillogram corresponding to Figure G.3 –Example of the required TRVs to be applied between the terminals of the unit(s) under test and between the live parts and the insulated enclosure
Figure G.7 – Example of a capacitive current injection circuit with enclosure of the circuit-breaker energized
Figure G.8 – Example of a capacitive synthetic circuit using two power-frequency circuits and with the enclosure of the circuit-breaker energized
Figure G.9 – Example of a capacitive synthetic current injection circuit – Unit testing on half a pole of a circuit-breaker with two units per pole – Enclosure energized with DC voltage
Figure G.10 – Example of a synthetic making circuit for out-of-phase tests
Annex H (informative) Step-by-step method to prolong arcing
Figure H.1 – Example of a re-ignition circuit diagram for prolonging arc-duration
Figure H.2 – Example of waveforms obtained during a symmetrical test using the circuit in Figure H.1
Annex I (informative) Synthetic methods for capacitive current tests [Go to Page]
I.1 General
I.2 Recovery voltage
I.3 Combined current and voltage circuits
I.4 Making tests
I.5 Current chopping
I.6 Examples test circuits
Figure I.1 – Power-frequency circuits in parallel
Figure I.2 – Current injection circuit
Figure I.3 – Power-frequency current injection circuit
Figure I.4 – Current injection circuit, recovery voltage applied to both terminals of the circuit-breaker
Figure I.5 – Current injection circuit with decay compensation
Figure I.6 – LC oscillating circuit
Figure I.7 – Inrush making current test circuit
Annex J (normative) Synthetic test methods for circuit-breakers with opening resistors [Go to Page]
J.1 General
J.2 Conditions [Go to Page]
J.2.1 General
J.2.2 Transient recovery voltage interval
J.2.3 Power-frequency recovery voltage interval
J.3 Multiple step test procedure [Go to Page]
J.3.1 General
J.3.2 Test to verify the re-ignition behaviour of the making and breaking unit
J.3.3 Test to verify the re-ignition behaviour of the making and breaking unit during short circuit test duties with any test method
Figure J.1 – Test circuit to verify re-ignition behaviour of the making and breaking unit using current injection method [Go to Page]
[Go to Page]
J.3.4 Tests on resistor switch(s)
Figure J.2 – Test circuit to verify re-ignition behaviour of the making and breaking unit [Go to Page]
J.4 Test requirements [Go to Page]
J.4.1 General
Figure J.3 – Test circuit on the resistor switch [Go to Page]
[Go to Page]
J.4.2 Testing of the making and breaking unit
Figure J.4 – Example of test circuit for capacitive current switching tests on the making and breaking unit [Go to Page]
[Go to Page]
J.4.3 Testing of the resistor switch
J.4.4 Test of the resistor stack
Figure J.5 – Example of test circuit for capacitive current switching tests on the resistor switch
Annex K (informative) Combination of current injection and voltage injection methods [Go to Page]
K.1 Current injection methods
K.2 Voltage injection methods
K.3 Combined current and voltage injection circuits [Go to Page]
K.3.1 General
K.3.2 Combined current and voltage injection circuit with application of full test voltage to earth
K.3.3 Combined current and voltage injection circuit with separated application of test voltage
Figure K.1 – Example of combined current and voltage injection circuit with application of full test voltage to earth
Figure K.2 – Example of combined current and voltage injection circuit with separated application of test voltage
Bibliography [Go to Page]

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