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IEEE Standard for Universal Verification Methodology Language Reference Manual (Redline), 2020
- IEEE Std 1800.2™-2020 Front Cover
- Title page
- Important Notices and Disclaimers Concerning IEEE Standards Documents
- Participants
- Introduction
- Contents
- 1. Overview [Go to Page]
- 1.1 Scope
- 1.2 Purpose
- 1.3 Word usage
- 1.4 Conventions used [Go to Page]
- 1.4.1 Visual cues (meta-syntax)
- 1.4.2 Return values
- 1.4.3 Inheritance
- 1.4.4 Operation order on equivalent data objects
- 1.4.5 uvm_pkg
- 1.4.6 Random stability
- 2. Normative references
- 3. Definitions, acronyms, and abbreviations [Go to Page]
- 3.1 Definitions
- 3.2 Acronyms and abbreviations
- 4. Universal Verification Methodology (UVM) class reference
- 5. Base classes [Go to Page]
- 5.1 Overview
- 5.2 uvm_void
- 5.3 uvm_object [Go to Page]
- 5.3.1 Class declaration
- 5.3.2 Common methods
- 5.3.3 Seeding
- 5.3.4 Identification
- 5.3.5 Creation
- 5.3.6 Printing
- 5.3.7 Recording
- 5.3.8 Copying
- 5.3.9 Comparing
- 5.3.10 Packing
- 5.3.11 Unpacking
- 5.3.12 Configuration
- 5.3.13 Field operations
- 5.3.14 Active policy
- 5.4 uvm_transaction [Go to Page]
- 5.4.1 Class declaration
- 5.4.2 Methods
- 5.5 uvm_port_base #(IF) [Go to Page]
- 5.5.1 Class declaration
- 5.5.2 Methods
- 5.6 uvm_time [Go to Page]
- 5.6.1 Class declaration
- 5.6.2 Common methods
- 5.7 uvm_field_op [Go to Page]
- 5.7.1 Class declaration
- 5.7.2 Methods
- 6. Reporting classes [Go to Page]
- 6.1 Overview
- 6.2 uvm_report_message [Go to Page]
- 6.2.1 Class declaration
- 6.2.2 Common methods
- 6.2.3 Infrastructure references
- 6.2.4 Message fields
- 6.3 uvm_report_object [Go to Page]
- 6.3.1 Class declaration
- 6.3.2 Common methods
- 6.3.3 Reporting
- 6.3.4 Verbosity configuration
- 6.3.5 Action configuration
- 6.3.6 File configuration
- 6.3.7 Override configuration
- 6.3.8 Report handler configuration
- 6.4 uvm_report_handler [Go to Page]
- 6.4.1 Class declaration
- 6.4.2 Common methods
- 6.4.3 Verbosity configuration
- 6.4.4 Action configuration
- 6.4.5 File configuration
- 6.4.6 Override configuration
- 6.4.7 Message processing
- 6.5 Report server [Go to Page]
- 6.5.1 uvm_report_server
- 6.5.2 uvm_default_report_server
- 6.6 uvm_report_catcher [Go to Page]
- 6.6.1 Class declaration
- 6.6.2 Common methods
- 6.6.3 Current message state
- 6.6.4 Change message state
- 6.6.5 Callback interface
- 6.6.6 Reporting
- 7. Recording classes [Go to Page]
- 7.1 uvm_tr_database [Go to Page]
- 7.1.1 Class declaration
- 7.1.2 Common methods
- 7.1.3 Database API
- 7.1.4 Stream API
- 7.1.5 Link API
- 7.1.6 Implementation agnostic API
- 7.2 uvm_tr_stream [Go to Page]
- 7.2.1 Class declaration
- 7.2.2 Common methods
- 7.2.3 Introspection API
- 7.2.4 Stream API
- 7.2.5 Transaction recorder API
- 7.2.6 Handles
- 7.2.7 Implementation agnostic API
- 7.3 UVM links [Go to Page]
- 7.3.1 uvm_link_base
- 7.3.2 uvm_parent_child_link
- 7.3.3 uvm_cause_effect_link
- 7.3.4 uvm_related_link
- 8. Factory classes [Go to Page]
- 8.1 Overview
- 8.2 Factory component and object wrappers [Go to Page]
- 8.2.1 Introduction
- 8.2.2 type_id
- 8.2.3 uvm_component_registry #(T,Tname)
- 8.2.4 uvm_object_registry #(T,Tname)
- 8.2.5 Abstract registries
- 8.3 UVM factory [Go to Page]
- 8.3.1 uvm_factory
- 8.3.2 uvm_object_wrapper
- 8.3.3 uvm_default_factory
- 9. Phasing [Go to Page]
- 9.1 Overview
- 9.2 Implementation [Go to Page]
- 9.2.1 Class hierarchy
- 9.2.2 Phasing related classes
- 9.2.3 Common and run-time phases
- 9.3 Phasing definition classes [Go to Page]
- 9.3.1 uvm_phase
- 9.3.2 uvm_phase_state_change
- 9.3.3 uvm_phase_cb
- 9.4 uvm_domain [Go to Page]
- 9.4.1 Class declaration
- 9.4.2 Methods
- 9.5 uvm_bottomup_phase [Go to Page]
- 9.5.1 Class declaration
- 9.5.2 Methods
- 9.6 uvm_task_phase [Go to Page]
- 9.6.1 Class declaration
- 9.6.2 Methods
- 9.7 uvm_topdown_phase [Go to Page]
- 9.7.1 Class declaration
- 9.7.2 Methods
- 9.8 Predefined phases [Go to Page]
- 9.8.1 Common phases
- 9.8.2 UVM run-time phases
- 10. Synchronization classes [Go to Page]
- 10.1 Event classes [Go to Page]
- 10.1.1 uvm_event_base
- 10.1.2 uvm_event#(t)
- 10.2 uvm_event_callback [Go to Page]
- 10.2.1 Class declaration
- 10.2.2 Methods
- 10.3 uvm_barrier [Go to Page]
- 10.3.1 Class declaration
- 10.3.2 Methods
- 10.4 Pool classes [Go to Page]
- 10.4.1 uvm_event_pool
- 10.4.2 uvm_barrier_pool
- 10.5 Objection mechanism [Go to Page]
- 10.5.1 uvm_objection
- 10.5.2 uvm_objection_callback
- 10.6 uvm_heartbeat [Go to Page]
- 10.6.1 Class declaration
- 10.6.2 Methods
- 10.7 Callbacks classes [Go to Page]
- 10.7.1 uvm_callback
- 10.7.2 uvm_callbacks #(T,CB)
- 11. Container classes [Go to Page]
- 11.1 Overview
- 11.2 uvm_pool #(KEY,T) [Go to Page]
- 11.2.1 Class declaration
- 11.2.2 Methods
- 11.3 uvm_queue #(T) [Go to Page]
- 11.3.1 Class declaration
- 11.3.2 Methods
- 12. UVM TLM interfaces [Go to Page]
- 12.1 Overview
- 12.2 UVM TLM 1 [Go to Page]
- 12.2.1 General
- 12.2.2 Unidirectional interfaces and ports
- 12.2.3 Bidirectional interfaces and ports
- 12.2.4 uvm_tlm_if_base #(T1,T2)
- 12.2.5 Port classes
- 12.2.6 Export classes
- 12.2.7 Implementation (imp) classes
- 12.2.8 FIFO classes
- 12.2.9 Channel classes
- 12.2.10 Analysis ports
- 12.3 UVM TLM 2 [Go to Page]
- 12.3.1 General
- 12.3.2 uvm_tlm_if: transport interfaces
- 12.3.3 Enumerations
- 12.3.4 Generic payload and extensions
- 12.3.5 Sockets
- 12.3.6 Port classes
- 12.3.7 Export classes
- 12.3.8 Implementation (imp) classes imps
- 12.3.9 uvm_tlm_time
- 13. Predefined component classes [Go to Page]
- 13.1 uvm_component [Go to Page]
- 13.1.1 Class declaration
- 13.1.2 Common methods
- 13.1.3 Hierarchy interface
- 13.1.4 Phasing interface
- 13.1.5 Configuration interface
- 13.1.6 Objection interface
- 13.1.7 Recording interface
- 13.1.8 Other interfaces
- 13.2 uvm_test [Go to Page]
- 13.2.1 Class declaration
- 13.2.2 Methods
- 13.3 uvm_env [Go to Page]
- 13.3.1 Class declaration
- 13.3.2 Methods
- 13.4 uvm_agent [Go to Page]
- 13.4.1 Class declaration
- 13.4.2 Methods
- 13.5 uvm_monitor [Go to Page]
- 13.5.1 Class declaration
- 13.5.2 Methods
- 13.6 uvm_scoreboard [Go to Page]
- 13.6.1 Class declaration
- 13.6.2 Methods
- 13.7 uvm_driver #(REQ,RSP) [Go to Page]
- 13.7.1 Class declaration
- 13.7.2 Ports
- 13.7.3 Methods
- 13.8 uvm_push_driver #(REQ,RSP) [Go to Page]
- 13.8.1 Class declaration
- 13.8.2 Ports
- 13.8.3 Methods
- 13.9 uvm_subscriber [Go to Page]
- 13.9.1 Class declaration
- 13.9.2 Ports
- 13.9.3 Methods
- 14. Sequence classes [Go to Page]
- 14.1 uvm_sequence_item [Go to Page]
- 14.1.1 Class declaration
- 14.1.2 Common fields
- 14.1.3 Reporting interface
- 14.2 uvm_sequence_base [Go to Page]
- 14.2.1 Class declaration
- 14.2.2 Common methods
- 14.2.3 Sequence execution
- 14.2.4 Run-time phasing
- 14.2.5 Sequence control
- 14.2.6 Sequence item execution
- 14.2.7 Response API
- 14.3 uvm_sequence #(REQ,RSP) [Go to Page]
- 14.3.1 Class declaration
- 14.3.2 Variables
- 14.3.3 Methods
- 14.4 uvm_sequence_library [Go to Page]
- 14.4.1 Class declaration
- 14.4.2 Example
- 14.4.3 Common methods
- 14.4.4 Sequence selection
- 14.4.5 Sequence registration
- 15. Sequencer classes [Go to Page]
- 15.1 Overview [Go to Page]
- 15.1.1 Sequencer variants
- 15.1.2 Sequence item ports
- 15.2 Sequencer interface [Go to Page]
- 15.2.1 uvm_sqr_if_base #(T1,T2)
- 15.2.2 Sequence item pull ports
- 15.3 uvm_sequencer_base [Go to Page]
- 15.3.1 Class declaration
- 15.3.2 Methods
- 15.3.3 Requests
- 15.3.4 Responses
- 15.3.5 Default sequence
- 15.4 Common sequencer API [Go to Page]
- 15.4.1 Method
- 15.4.2 Request
- 15.4.3 Responses
- 15.5 uvm_sequencer #(REQ,RSP) [Go to Page]
- 15.5.1 Class declaration
- 15.5.2 Methods
- 15.6 uvm_push_sequencer #(REQ,RSP) [Go to Page]
- 15.6.1 Class declaration
- 15.6.2 Ports
- 15.6.3 Methods
- 16. Policy classes [Go to Page]
- 16.1 uvm_policy [Go to Page]
- 16.1.1 Class declaration
- 16.1.2 Methods
- 16.1.3 Active object
- 16.1.4 recursion_state_e
- 16.2 uvm_printer [Go to Page]
- 16.2.1 Class declaration
- 16.2.2 Methods
- 16.2.3 Methods for printer usage
- 16.2.4 Methods for printer subtyping
- 16.2.5 Methods for printer configuration
- 16.2.6 Methods for object print control
- 16.2.7 Element stack
- 16.2.8 uvm_printer_element
- 16.2.9 uvm_printer_element_proxy
- 16.2.10 uvm_table_printer
- 16.2.11 uvm_tree_printer
- 16.2.12 uvm_line_printer
- 16.3 uvm_comparer [Go to Page]
- 16.3.1 Class declaration
- 16.3.2 Methods
- 16.3.3 Methods for comparer usage
- 16.3.4 Methods for comparer configuration
- 16.3.5 Methods for comparer reporting control
- 16.3.6 Methods for object compare control
- 16.4 uvm_recorder [Go to Page]
- 16.4.1 Class declaration
- 16.4.2 Methods for recorder configuration
- 16.4.3 Introspection API
- 16.4.4 Transaction recorder API
- 16.4.5 Handles
- 16.4.6 Attribute recording
- 16.4.7 Implementation agnostic API
- 16.5 uvm_packer [Go to Page]
- 16.5.1 Class declaration
- 16.5.2 Methods
- 16.5.3 Methods for packer subtyping
- 16.5.4 Packing and unpacking
- 16.6 uvm_copier [Go to Page]
- 16.6.1 Class declaration
- 16.6.2 Methods
- 16.6.3 Methods for object copy control
- 16.6.4 Methods for copier usage
- 17. Register layer [Go to Page]
- 17.1 Overview
- 17.2 Global declarations [Go to Page]
- 17.2.1 Types
- 17.2.2 Enumerations
- 17.2.3 uvm_hdl_path_concat
- 18. Register model [Go to Page]
- 18.1 uvm_reg_block [Go to Page]
- 18.1.1 Class declaration
- 18.1.2 Methods
- 18.1.3 Introspection
- 18.1.4 Coverage
- 18.1.5 Access
- 18.1.6 Back door
- 18.2 uvm_reg_map [Go to Page]
- 18.2.1 Class declaration
- 18.2.2 Common methods
- 18.2.3 Methods
- 18.2.4 Introspection
- 18.2.5 Bus access
- 18.3 uvm_reg_file [Go to Page]
- 18.3.1 Class declaration
- 18.3.2 Methods
- 18.3.3 Introspection
- 18.3.4 Back door
- 18.4 uvm_reg [Go to Page]
- 18.4.1 Class declaration
- 18.4.2 Methods
- 18.4.3 Introspection
- 18.4.4 Access
- 18.4.5 Front door
- 18.4.6 Back door
- 18.4.7 Coverage
- 18.4.8 Callbacks
- 18.5 uvm_reg_field [Go to Page]
- 18.5.1 Class declaration
- 18.5.2 Member variables
- 18.5.3 Methods
- 18.5.4 Introspection
- 18.5.5 Access
- 18.5.6 Callbacks
- 18.6 uvm_mem [Go to Page]
- 18.6.1 Class declaration
- 18.6.2 Variables
- 18.6.3 Methods
- 18.6.4 Introspection
- 18.6.5 HDL access
- 18.6.6 Front door
- 18.6.7 Back door
- 18.6.8 Coverage
- 18.6.9 Callbacks
- 18.7 uvm_reg_indirect_data [Go to Page]
- 18.7.1 Class declaration
- 18.7.2 Methods
- 18.8 uvm_reg_fifo [Go to Page]
- 18.8.1 Class declaration
- 18.8.2 Common variables
- 18.8.3 Methods
- 18.8.4 Introspection
- 18.8.5 Access
- 18.9 uvm_vreg [Go to Page]
- 18.9.1 Class declaration
- 18.9.2 uvm_vreg_cbs
- 18.10 uvm_vreg_field [Go to Page]
- 18.10.1 Class declaration
- 18.10.2 Methods
- 18.10.3 Introspection
- 18.10.4 HDL access
- 18.10.5 Callbacks
- 18.10.6 uvm_vreg_field_cbs
- 18.11 uvm_reg_cbs [Go to Page]
- 18.11.1 Class declaration
- 18.11.2 Methods
- 18.11.3 Types
- 18.11.4 uvm_reg_read_only_cbs
- 18.11.5 uvm_reg_write_only_cbs
- 18.12 uvm_mem_mam [Go to Page]
- 18.12.1 Class declaration
- 18.12.2 Types
- 18.12.3 Variables
- 18.12.4 Methods
- 18.12.5 Memory management
- 18.12.6 Introspection
- 18.12.7 uvm_mem_region
- 18.12.8 uvm_mem_mam_policy
- 18.12.9 uvm_mem_mam_cfg
- 19. Register layer interaction with the design [Go to Page]
- 19.1 Generic register operation descriptors [Go to Page]
- 19.1.1 uvm_reg_item
- 19.1.2 uvm_reg_bus_op
- 19.2 Classes for adapting between register and bus operations [Go to Page]
- 19.2.1 uvm_reg_adapter
- 19.2.2 uvm_reg_tlm_adapter
- 19.3 uvm_reg_predictor [Go to Page]
- 19.3.1 Class declaration
- 19.3.2 Variables
- 19.3.3 Methods
- 19.4 Register sequence classes [Go to Page]
- 19.4.1 uvm_reg_sequence
- 19.4.2 uvm_reg_frontdoor
- 19.5 uvm_reg_backdoor [Go to Page]
- 19.5.1 Class declaration
- 19.5.2 Methods
- 19.6 UVM HDL backdoor access support routines [Go to Page]
- 19.6.1 Variables
- 19.6.2 Methods
- Annex A (informative) Bibliography
- Annex B (normative) Macros and defines [Go to Page]
- B.1 Report macros
- B.2 Utility and field macros for components and objects
- B.3 Sequence-related macros
- B.4 Callback macros
- B.5 UVM TLM implementation port declaration macros
- B.6 Size defines
- B.7 UVM version globals
- Annex C (normative) Configuration and resource classes [Go to Page]
- C.1 Overview
- C.2 Resources
- C.3 UVM resource database
- C.4 UVM configuration database
- Annex D (normative) Convenience classes, interface, and methods [Go to Page]
- D.1 uvm_callback_iter
- D.2 Component interfaces
- D.3 uvm_reg_block access methods
- D.4 Callback typedefs
- Annex E (normative) Test sequences [Go to Page]
- E.1 uvm_reg_hw_reset_seq
- E.2 Bit bashing test sequences
- E.3 Register access test sequences
- E.4 Shared register and memory access test sequences
- E.5 Memory access test sequences
- E.6 Memory walking-ones test sequences
- E.7 uvm_reg_mem_hdl_paths_seq
- E.8 uvm_reg_mem_built_in_seq
- Annex F (normative) Package scope functionality [Go to Page]
- F.1 Overview
- F.2 Types and enumerations
- F.3 Methods and types
- F.4 Core service
- F.5 Traversal
- F.6 uvm_run_test_callback
- F.7 uvm_root
- Annex G (normative) Command line arguments [Go to Page]
- G.1 Command line processing
- G.2 Built-in UVM-aware command line arguments
- Annex H (normative) Deprecation [Go to Page]
- H.1 General
- H.2 Constructs that have been deprecated
- Back cover [Go to Page]
